搜索资源列表
A_CPU_verilog
- 这是一个verilog编写的CPU程序,希望对初学者有所帮组吧-a cpu
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能,有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
CACPU
- basic cpu design in verilog
udp_send1
- 基于FPGA的UDP硬件协议栈, 全部用SystemVerilog写的,不需CPU参与,包括独立的MAC模块。 支持外部phy的配置,支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
mips
- Verilog语言开发的基于mips指令集的流水线cpu,只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
sc_computer_2
- Verilog单周期CPU实现,可以实现简单的mips指令,附Verilog源码-Verilog achieve single-cycle CPU
pcpu_handle_mem
- Verilog实现五级流水线CPU,hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码,当然有一些模块是在quartus中直接编辑波形测试的,所以没有响应的测试脚本文件。 tri_state_port的测试还未完成,test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档: PIC10_RISC_Design.pdf:原文(verilog代码基本都来自原文,对一部分进行了改进),这篇文章写
m_cycle_mips
- verilog设计的5状态多周期mips -multiple cycle mips CPU design of Verilog
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程,可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元,外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008),可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
myCpu2
- CPU硬件实现,能运行基本程序,FPGA,verilog源码-CPU hardware implementation, can run the basic procedures, FPGA, Verilog source code
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU,含代码工程文件和相关设计说明文档,比较详细。-verilog HDL, 32 MIPS pipeline CPU
idwt
- Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse
ECOP
- 关于verilog语言的多周期cpu实现的方式(Multi cycle CPU implementation)
RSIC
- 包含控制部分和逻辑运算部分的精简CPU,适合verilog的初学者(Ti's a CPU which contain the part of chontrol and Arithmetic logic,it's approximate for people who contact veriolg with short time)
uart_design
- UART设计的VERILOG代码,具有FIFO功能,能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
soc_sram_func
- 利用verilog编写的32位 MIPS指令集CPU,sram接口,已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)
risc_cpu
- 8 位cpu的verilog实现 verilog代码